Publications

By venue:

Conferences: HPCA 2019 FPGA 2019 FPL 2018 ISCA 2018 OSDI 2016 NSDI 2013

Journals: IEEE Micro 2019.3 (Top Picks 2018)

Workshops: CARRV 2018 AACBB 2018 MES 2016

Tech Reports: Master’s Thesis EECS TR 2016-17 EECS TR 2015-264 EECS TR 2015-263

Selected Pubs:

ISCA 2018: “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”. (link)
Selected as the Communications of the ACM Research Highlights Nominee from ISCA 2018. (link)
Paper PDF | Slides PDF | Open-source on GitHub | Docs | IEEE Xplore | BibTeX

All Pubs, Chronologically:

IEEE Micro 2019.3 (Top Picks 2018): “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.
Article PDF | IEEE Xplore | Micro Top Picks 2018 Introduction | Original Paper

HPCA 2019: “FPGA Accelerated INDEL Realignment in the Cloud”

Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A. Patterson, and Anthony D. Joseph, “FPGA Accelerated INDEL Realignment in the Cloud”, In proceedings of the 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2019, Washington D.C, February 2019.
Preprint PDF

FPGA 2019: “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”

David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”, In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2018.
Paper PDF

FPL 2018: “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović, “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”, In proceedings of the 28th International Conference on Field Programmable Logic & Applications (FPL 2018), Dublin, Ireland, August 2018.
Paper PDF

ISCA 2018: “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”. (link)
Selected as the Communications of the ACM Research Highlights Nominee from ISCA 2018. (link)
Paper PDF | Slides PDF | Open-source on GitHub | Docs | IEEE Xplore | BibTeX

Master’s Thesis: “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, Master’s Thesis, EECS Department, University of California, Berkeley, May 2018.
PDF | Web

CARRV 2018: “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović. “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”. Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018). Los Angeles, June 2018.
Paper PDF

AACBB 2018: “Accelerating Duplicate Marking In The Cloud”

Lisa Wu, Frank Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanović, David Patterson and Anthony Joseph. “Accelerating Duplicate Marking In The Cloud”. Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), at the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2018), Vienna, Austria, February, 2018.

OSDI 2016: “Network Requirements for Resource Disaggregation”

Peter X. Gao, Akshay Narayan, Sagar Karandikar, Joao Carreira, Sangjin Han, Rachit Agarwal, Sylvia Ratnasamy, and Scott Shenker. “Network Requirements for Resource Disaggregation”, In proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI), USENIX, Savannah, GA, November 2016.
Paper PDF

MES 2016: “Vector Processors for Energy-Efficient Embedded Systems”

Daniel Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar, and Krste Asanović. “Vector Processors for Energy-Efficient Embedded Systems”. In proceedings of the 4th ACM International Workshop on Manycore Embedded Systems (MES), ACM, Seoul, Korea, June 2016.

Berkeley EECS TR 2016-17: “The Rocket Chip Generator”

Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman. “The Rocket Chip Generator”. EECS Department, University of California, Berkeley. April 2016.
PDF

Berkeley EECS TR 2015-264: Hwacha Preliminary Evaluation Results, Version 3.8.1

Yunsup Lee, Colin Schmidt, Sagar Karandikar, Daniel Dabbelt, Albert Ou and Krste Asanović. “Hwacha Preliminary Evaluation Results, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015.
PDF

Berkeley EECS TR 2016-263: “The Hwacha Microarchitecture Manual, Version 3.8.1”

Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao and Krste Asanović. “The Hwacha Microarchitecture Manual, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015.
PDF

NSDI 2013: “BOSS: Building Operating System Services”

Stephen Dawson-Haggerty, Andrew Krioukov, Jay Taneja, Sagar Karandikar, Gabe Fierro, Nikita Kitaev, and David Culler. “BOSS: Building Operating System Services”. In proceedings of the 10th USENIX Symposium on Networked Systems Design and Implementation (NSDI), USENIX, Lombard, IL, April 2013.
Paper PDF