: “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”
Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović, “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”, To appear, in proceedings of the 28th International Conference on Field Programmable Logic & Applications (FPL 2018), Dublin, Ireland, August 2018.
Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018. PDF Preprint | Slides PDF | Open-source on GitHub | Docs
Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović. “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”. Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018). Los Angeles, June 2018. PDF
Lisa Wu, Frank Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanović, David Patterson and Anthony Joseph. “Accelerating Duplicate Marking In The Cloud”. Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), at the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2018), Vienna, Austria, February, 2018.
Peter X. Gao, Akshay Narayan, Sagar Karandikar, Joao Carreira, Sangjin Han, Rachit Agarwal, Sylvia Ratnasamy, and Scott Shenker. “Network Requirements for Resource Disaggregation”, In proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI), USENIX, Savannah, GA, November 2016. PDF
Daniel Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar, and Krste Asanović. “Vector Processors for Energy-Efficient Embedded Systems”. In proceedings of the 4th ACM International Workshop on Manycore Embedded Systems (MES), ACM, Seoul, Korea, June 2016.
Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman. “The Rocket Chip Generator”. EECS Department, University of California, Berkeley. April 2016. PDF
Yunsup Lee, Colin Schmidt, Sagar Karandikar, Daniel Dabbelt, Albert Ou and Krste Asanović. “Hwacha Preliminary Evaluation Results, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015. PDF
Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao and Krste Asanović. “The Hwacha Microarchitecture Manual, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015. PDF
Stephen Dawson-Haggerty, Andrew Krioukov, Jay Taneja, Sagar Karandikar, Gabe Fierro, Nikita Kitaev, and David Culler. “BOSS: Building Operating System Services”. In proceedings of the 10th USENIX Symposium on Networked Systems Design and Implementation (NSDI), USENIX, Lombard, IL, April 2013. PDF