My research focuses on identifying and exploiting hardware-software co-design opportunities in warehouse-scale computers to improve datacenter performance, energy efficiency, and total cost of ownership. My work spans various areas including hardware accelerator and server system-on-chip design for hyperscale systems, system optimization and profiling, and agile, open-source hardware development methodologies.
I lead the FireSim project, which enables cycle-accurate simulation of thousand-node clusters interconnected by high-performance networks using FPGAs in the cloud. FireSim enables prototyping datacenters with full control over the datacenter’s compute hardware (cycle-exactly simulating tapeout-friendly RTL), network, and software (running complete operating systems and applications), as described in our ISCA ‘18 paper. FireSim was selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2018, as the CACM Research Highlights Nominee from ISCA 2018, and for the ISCA@50 25-year Retrospective 1996-2020 collection.
FireSim is open-source and includes extensive documentation, covering use cases from cycle-exact pre-silicon modeling of individual SoC designs to modeling massive scale-out systems. FireSim has been used in over 50 publications from authors at over 20 academic and industrial institutions across various areas including computer architecture, systems, networking, security, scientific computing, algorithms, HPC, circuits, design automation, and more (see User Publications on the FireSim website). FireSim has also been used in the development of commercially-available silicon.
Our FirePerf ASPLOS 2020 paper added out-of-band performance profiling features to FireSim, facilitating rapid improvements in networking performance on RISC-V server SoCs, including commercially available products.
I also lead the Hyperscale SoC project, working on techniques to address system-level overheads in WSCs (e.g., the “datacenter taxes”) using data-driven HW/SW co-design, combining fleet-wide profiling of a major cloud provider (Google) with agile, open-source hardware development methodologies. Tackling serialization and deserialization overheads, our paper at MICRO 2021 presented a detailed profiling study of protocol buffers usage in Google’s datacenter fleet and built/open-sourced HyperProtoBench, a benchmark suite representative of key protobuf-user services at Google. This work also produced an open-source hardware-accelerator for protocol buffers and evaluated it cycle-exactly in FireSim (booting Linux and running HyperProtoBench), demonstrating significant speedups compared to a Xeon server. This paper won the Distinguished Artifact Award at MICRO 2021 and was selected as an Honorable Mention in IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2021. Our recent paper at ISCA 2023 tackles another critical system-level operation in WSCs: general-purpose lossless compression and decompression.
Additionally, I co-lead the Chipyard project, an open-source framework for agile RISC-V SoC design, implementation, and evaluation. Chipyard provides a customizable foundation for building complex SoCs for specialized domains, including Hyperscale SoC.
In Fall 2023, I created/led a new graduate course on hyperscale computing at UC Berkeley, CS294-252. I have also been a lecturer and many-time TA for UC Berkeley’s CS61C, a sophomore-level computer architecture/systems course. As a CS61C TA, I received UC Berkeley’s Outstanding Graduate Student Instructor (TA) award. I was also selected as a 2022 DARPA Riser. I have interned at Google and SiFive. I received a B.S. in Electrical Engineering and Computer Sciences and an M.S. in Computer Science from UC Berkeley.
The best way to reach me is at sagark at eecs dot berkeley dot edu.