I am an incoming Assistant Professor in the Electrical Engineering and Computer Sciences department at UC Berkeley, starting in July 2025. Currently, I am wrapping up my Ph.D. in Computer Architecture at UC Berkeley, advised by Krste Asanović. I am also currently a Student Researcher at Google, where I work with Parthasarathy Ranganathan. The best way to reach me is at sagark at eecs dot berkeley dot edu.

My research focuses on hardware/software co-design for hyperscale cloud systems to improve hyperscale datacenter/warehouse-scale computer (WSC) performance, energy efficiency, and total cost of ownership. My work spans various areas including hardware accelerator and server system-on-chip design for hyperscale systems, system optimization and profiling, and agile, open-source hardware development methodologies.

My work has received several recognitions, including an ISCA@50 25-year Retrospective selection, an IEEE Micro Top Picks selection, an IEEE Micro Top Picks honorable mention, and the MICRO ‘21 Distinguished Artifact Award. My work is also widely used in the community, having been used in numerous peer-reviewed publications, in the development of commercially available chips, and as a standard host platform for DARPA/IARPA programs. I also received the Berkeley EECS David J. Sakrison Memorial Prize for outstanding graduate research, the UC Berkeley Outstanding Graduate Student Instructor (TA) Award, and was selected as a DARPA Riser.

Active Research Projects

Below are some highlights from ongoing projects. Additional publications and projects can be found here.

I lead the FireSim project, which enables cycle-accurate simulation of thousand-node clusters interconnected by high-performance networks using FPGAs in the cloud. FireSim enables prototyping datacenters with full control over the datacenter’s compute hardware (cycle-exactly simulating tapeout-friendly RTL), network, and software (running complete operating systems and applications), as described in our ISCA ‘18 paper. FireSim was selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2018, as the CACM Research Highlights Nominee from ISCA 2018, and for the ISCA@50 25-year Retrospective 1996-2020 collection.

FireSim is open-source and includes extensive documentation, covering use cases from cycle-exact pre-silicon modeling of individual SoC designs to modeling massive scale-out systems. FireSim has been used in over 50 publications from authors at over 20 academic and industrial institutions across various areas including computer architecture, systems, networking, security, scientific computing, algorithms, HPC, circuits, design automation, and more (see User Publications on the FireSim website). FireSim has also been used in the development of commercially-available silicon.

Our FirePerf ASPLOS 2020 paper added out-of-band performance profiling features to FireSim, facilitating rapid improvements in networking performance on RISC-V server SoCs, including commercially available products.

We’ve recently extended FireSim to support partitioning large, monolithic RTL designs across multiple FPGAs, in our FireAxe paper at ISCA 2024. This paper received a Distinguished Artifact Award at ISCA 2024.

I also lead the Hyperscale SoC project, working on techniques to address system-level overheads in WSCs using data-driven HW/SW co-design, combining fleet-wide profiling of a major cloud provider (Google) with agile, open-source hardware development methodologies. Tackling serialization and deserialization overheads, our paper at MICRO 2021 presented a detailed profiling study of protocol buffers usage in Google’s datacenter fleet and built/open-sourced HyperProtoBench, a benchmark suite representative of key protobuf-user services at Google. This work also produced an open-source hardware-accelerator for protocol buffers and evaluated it cycle-exactly in FireSim (booting Linux and running HyperProtoBench), demonstrating significant speedups compared to a Xeon server. This paper won the Distinguished Artifact Award at MICRO 2021 and was selected as an Honorable Mention in IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2021. Our recent paper at ISCA 2023 tackles another critical system-level operation in WSCs: general-purpose lossless compression and decompression.

I co-lead the Chipyard project, a widely used open-source framework for agile RISC-V System-on-Chip (SoC) design, implementation, and evaluation. Chipyard allows users to compose complex systems from a large collection of parameterized, generator-based IP blocks such as in-order and out-of-order RISC-V cores, uncore components, peripherals, accelerators, user-supplied IP, and more. Chipyard also includes software that runs on the generated SoCs, ranging from firmware, bootloaders, and bare-metal testing infrastructure to several compatible Linux distributions (e.g., Buildroot, Ubuntu, and more). Users can customize any component of a Chipyard-generated system (including adding their own Chisel or SystemVerilog IP blocks) and push the SoC through high-performance FPGA-accelerated simulation flows (e.g. FireSim), software RTL simulation flows, and automated ASIC flows (e.g. Hammer). With high-levels of automation and integration, Chipyard enables users to productively iterate on complex specialized designs, such as Hyperscale SoC.