I am a Ph.D. student in Computer Science at the University of California, Berkeley, focusing in Computer Architecture and Systems. I work in the Berkeley Architecture Research group and the ADEPT and RISE Labs, advised by Krste Asanović. I am also a Student Researcher at Google, where I work with Parthasarathy Ranganathan.

My research focuses on hardware-software co-design opportunities in warehouse-scale computers, in order to improve datacenter performance and energy efficiency while reducing total cost of ownership. My work spans various areas including hardware accelerator and server system-on-chip design for hyperscale systems, system optimization and profiling, and agile, open-source hardware development methodologies.

I lead the FireSim project, which enables cycle-accurate simulation of thousand-node clusters interconnected by high-performance networks using FPGAs in the cloud. FireSim allows us to prototype a datacenter, with full control over the compute hardware (from RTL), network, and software (with complete operating systems and applications) in the datacenter at less than 500x slowdown over building the real thing (see the ISCA ‘18 paper for more). FireSim is open-source on GitHub and includes extensive documentation. To better understand the performance of systems we model and to enable better hardware/software co-design of these systems, our FirePerf ASPLOS 2020 paper added new out-of-band performance profiling features to FireSim.

FireSim was selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2018 and as the CACM Research Highlights Nominee from ISCA 2018. FireSim has also been used in published work from authors at over 20 academic and industrial institutions across various areas including Computer Architecture, Systems, Networking, Circuits, and Security (see User Publications on the FireSim website). FireSim has also been used in the development of shipping commercial silicon.

I also work on techniques to address system-level overheads in the hyperscale/WSC context (the “datacenter tax”). Our paper at MICRO 2021 presented a detailed study of one of these overheads in Google’s datacenter fleet, Protocol Buffers serialization and deserialization. As part of this paper, we also produced HyperProtoBench, an open-source benchmark representative of key protobuf-user services at Google and an open-source hardware accelerator for Protocol Buffers. This paper won the Distinguished Artifact Award at MICRO 2021 and was selected as an Honorable Mention in IEEE Micro’s “Top Picks from Computer Architecture Conferences” for 2021.

Some of the other projects I’ve worked on/contributed to in the past include: characterizing workloads in disaggregated datacenters, building hardware accelerators for WSC services, the Hwacha vector processor, the RISC-V QEMU port (now upstreamed), a JavaScript RISC-V Simulator, and other RISC-V-related infrastructure. More projects can be found on my publications page.

Previously, I was a lecturer and many-time TA for CS61C, a sophomore-level computer architecture/systems course at Berkeley. I also received a B.S. in Electrical Engineering and Computer Sciences and M.S. in Computer Science from Berkeley in May 2015 and May 2018 respectively. I have also previously interned at Google and SiFive.

The best way to reach me is at sagark at eecs dot berkeley dot edu.