Publications

Index of selected publications, by venue:

CDPU, ISCA 2023 (1) FireSim, ISCA@50 Retrospective ProtoAcc, MICRO 2021 FirePerf, ASPLOS 2020 FireSim, IEEE Micro 2019.3 (Top Picks 2018) FireSim, ISCA 2018

Index of all publications, by venue:

Conferences: ISCA 2024 ISCA 2023 (1) ISCA 2023 (2) MICRO 2021 ISPASS 2021 DAC 2020 (invited) ASPLOS 2020 ICCAD 2019 HPCA 2019 FPGA 2019 FPL 2018 ISCA 2018 OSDI 2016 NSDI 2013

Journals/Retrospectives: ISCA@50 Retrospective IEEE Micro 2021.4 IEEE Micro 2020.4 IEEE Micro 2019.3 (Top Picks 2018)

Workshops: CARRV 2019 CARRV 2018 AACBB 2018 MES 2016

Tech Reports: Master’s Thesis EECS TR 2016-17 EECS TR 2015-264 EECS TR 2015-263

All publications, chronologically:

ISCA 2024: “FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs”

Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolić, Yakun Sophia Shao, and Krste Asanović, “FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs”, In Proceedings of the 51st ACM/IEEE International Symposium on Computer Architecture (ISCA 2024), Buenos Aires, Argentina, June 2024.
Received a Distinguished Artifact Award at ISCA 2024.
Pre-print PDF | IEEE Xplore (coming soon)

ISCA 2023 (1): “CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems”

Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Yakun Sophia Shao, Borivoje Nikolić, Krste Asanović, and Parthasarathy Ranganathan, “CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems”, In Proceedings of the 50th ACM/IEEE International Symposium on Computer Architecture (ISCA 2023), Orlando, FL, USA, June 2023.
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF

ISCA 2023 (2): “Profiling Hyperscale Big Data Processing”

Abraham Gonzalez, Aasheesh Kolli, Samira Khan, Sihang Liu, Vidushi Dadu, Sagar Karandikar, Jichuan Chang, Krste Asanović, and Parthasarathy Ranganathan, “Profiling Hyperscale Big Data Processing”, In Proceedings of the 50th ACM/IEEE International Symposium on Computer Architecture (ISCA 2023), Orlando, FL, USA, June 2023.
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF

ISCA@50 Retrospective: “RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, In ISCA@50 Retrospective: 1996-2020, Edited by José F. Martínez and Lizy K. John, June 2023.
Retrospective Paper PDF | Original Paper

MICRO 2021: “A Hardware Accelerator for Protocol Buffers”

Sagar Karandikar, Chris Leary, Chris Kennelly, Jerry Zhao, Dinesh Parimi, Borivoje Nikolić, Krste Asanović, and Parthasarathy Ranganathan, “A Hardware Accelerator for Protocol Buffers”, In Proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54), Athens, Greece, October 2021.
Selected as an Honorable Mention in IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2021”. (link)
Selected as the Distinguished Artifact Award Winner at MICRO 2021. (link, link)
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF

IEEE Micro 2021.4: “Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim”

David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolić, Krste Asanović, “Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim”, IEEE Micro, vol. 41, no. 4, pp. 58-66, July-Aug 2021.
Pre-print PDF | IEEE Xplore

ISPASS 2021: “COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors”

Jerry Zhao, Abraham Gonzalez, Alon Amid, Sagar Karandikar and Krste Asanović, “COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors,” 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2021, pp. 310-320.
Pre-print PDF | IEEE Xplore

DAC 2020 (invited): “Invited: Chipyard - An Integrated SoC Research and Implementation Environment”

Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Jonathan Bachrach, Sophia Shao, Borivoje Nikolić, Krste Asanović, “Invited: Chipyard - An Integrated SoC Research and Implementation Environment”, 2020 57th ACM/IEEE Design Automation Conference (DAC), 2020, pp. 1-6.
Pre-print PDF | IEEE Xplore

IEEE Micro 2020.4: “Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs”

Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanović, Borivoje Nikolić, “Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs”, IEEE Micro, vol. 40, no. 4, pp. 10-21, July-Aug 2020.
Pre-print PDF | IEEE Xplore

ASPLOS 2020: “FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design”

Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, “FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design”, In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Lausanne, Switzerland, March 2020.
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF | Talk Video on YouTube | Open-source Docs

ICCAD 2019: “Centrifuge: Evaluating full-system HLS-generated heterogeneous-accelerator SoCs using FPGA-Acceleration”

Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanović, John Wawrzynek, “Centrifuge: Evaluating full-system HLS-generated heterogeneous-accelerator SoCs using FPGA-Acceleration”, In proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, November 2019.
Paper PDF

CARRV 2019: “Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research”

Sagar Karandikar, David Biancolin, Alon Amid, Nathan Pemberton, Albert Ou, Randy Katz, Borivoje Nikolić, Jonathan Bachrach and Krste Asanović. “Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research”. Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019). Phoenix, June 2019.
Paper PDF

IEEE Micro 2019.3 (Top Picks 2018): “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.
Article PDF | IEEE Xplore | Micro Top Picks 2018 Introduction | Original Paper

HPCA 2019: “FPGA Accelerated INDEL Realignment in the Cloud”

Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A. Patterson, and Anthony D. Joseph, “FPGA Accelerated INDEL Realignment in the Cloud”, In proceedings of the 25th IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2019, Washington D.C, February 2019.
Pre-print PDF

FPGA 2019: “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”

David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović, “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”, In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2019.
Paper PDF

FPL 2018: “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović, “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”, In proceedings of the 28th International Conference on Field Programmable Logic & Applications (FPL 2018), Dublin, Ireland, August 2018.
Paper PDF

CARRV 2018: “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović. “Debugging RISC-V Processors with FPGA-Accelerated RTL Simulation in the FPGA Cloud”. Second Workshop on Computer Architecture Research with RISC-V (CARRV 2018). Los Angeles, June 2018.
Paper PDF

ISCA 2018: “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA 2018), Los Angeles, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”. (link)
Selected as the Communications of the ACM Research Highlights Nominee from ISCA 2018. (link)
Selected for “ISCA@50 25-year Retrospective 1996-2020”. (link)
Paper PDF | Slides PDF | Open-source on GitHub | Docs | IEEE Xplore | BibTeX

Master’s Thesis: “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”

Sagar Karandikar, “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”, Master’s Thesis, EECS Department, University of California, Berkeley, May 2018.
PDF | Web

AACBB 2018: “Accelerating Duplicate Marking In The Cloud”

Lisa Wu, Frank Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanović, David Patterson and Anthony Joseph. “Accelerating Duplicate Marking In The Cloud”. Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB), at the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2018), Vienna, Austria, February, 2018.

OSDI 2016: “Network Requirements for Resource Disaggregation”

Peter X. Gao, Akshay Narayan, Sagar Karandikar, Joao Carreira, Sangjin Han, Rachit Agarwal, Sylvia Ratnasamy, and Scott Shenker. “Network Requirements for Resource Disaggregation”, In proceedings of the 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI), USENIX, Savannah, GA, November 2016.
Paper PDF

MES 2016: “Vector Processors for Energy-Efficient Embedded Systems”

Daniel Dabbelt, Colin Schmidt, Eric Love, Howard Mao, Sagar Karandikar, and Krste Asanović. “Vector Processors for Energy-Efficient Embedded Systems”. In proceedings of the 4th ACM International Workshop on Manycore Embedded Systems (MES), ACM, Seoul, Korea, June 2016.

Berkeley EECS TR 2016-17: “The Rocket Chip Generator”

Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman. “The Rocket Chip Generator”. EECS Department, University of California, Berkeley. April 2016.
PDF

Berkeley EECS TR 2015-264: Hwacha Preliminary Evaluation Results, Version 3.8.1

Yunsup Lee, Colin Schmidt, Sagar Karandikar, Daniel Dabbelt, Albert Ou and Krste Asanović. “Hwacha Preliminary Evaluation Results, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015.
PDF

Berkeley EECS TR 2016-263: “The Hwacha Microarchitecture Manual, Version 3.8.1”

Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao and Krste Asanović. “The Hwacha Microarchitecture Manual, Version 3.8.1”. EECS Department, University of California, Berkeley. December 2015.
PDF

NSDI 2013: “BOSS: Building Operating System Services”

Stephen Dawson-Haggerty, Andrew Krioukov, Jay Taneja, Sagar Karandikar, Gabe Fierro, Nikita Kitaev, and David Culler. “BOSS: Building Operating System Services”. In proceedings of the 10th USENIX Symposium on Networked Systems Design and Implementation (NSDI), USENIX, Lombard, IL, April 2013.
Paper PDF